Voltage-controlled (VC) spin-orbit-torque (SOT) magnetic random access memory (MRAM) is being considered as the next-generation magnetic memory with potential to achieve superior speed, power, and write error rates over existing MRAM technologies. By placing multiple VC devices on a single SOT bus, VC-SOT MRAM can also enable compact structures, in which multiple devices can be addressed individually yet programmed via a shared current. In this work, we propose two implementations of shared-current write: the horizontal shared current write (HSCW), which reduces the average SOT current per bit by the number of bits on the SOT bus, and the vertical shared current write (VSCW), which can further leverage data dependency for increased performance. We simulate the efficiency of the HSCW and VSCW using a Landau-Lifshitz-Gilbert (LLG)-based VC-SOT model and a 28-nm CMOS technology and show that HSCW and VSCW can achieve an energy saving of 74% and 40%-87%, respectively, in a 32-bit setting. Analysis of data patterns in common workloads finds that 40% of data share more than 85% common bits, for which VSCW can leverage for further improved performance.
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