Low Latency Design of Polar Decoder for Flash Memory

研究成果: Conference contribution

摘要

We propose a multiple error correction coding scheme with systematic polar code to enhance the data reliability and to prolong the endurance for flash memory. A line-based 2-bit simplified successive cancellation (SSC) decoder is integrated with a bit-permutation construction to lower the latency. The patterns of information bits and frozen bits are rearranged. The experimental results show that the hardware implementation of the SSC decoder with the codeword permutation speed up 8.1% compared to the prior design.

原文English
主出版物標題2021 IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781665433280
DOIs
出版狀態Published - 2021
事件8th IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021 - Penghu, Taiwan
持續時間: 2021 9月 152021 9月 17

出版系列

名字2021 IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021

Conference

Conference8th IEEE International Conference on Consumer Electronics-Taiwan, ICCE-TW 2021
國家/地區Taiwan
城市Penghu
期間21-09-1521-09-17

All Science Journal Classification (ASJC) codes

  • 人工智慧
  • 電腦科學應用
  • 電氣與電子工程
  • 控制和優化
  • 儀器

指紋

深入研究「Low Latency Design of Polar Decoder for Flash Memory」主題。共同形成了獨特的指紋。

引用此