摘要
This work proposes a hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) gate driver with a low-leakage capacitive coupling structure to reduce the delay of the clock signal. The proposed circuit suppresses the fluctuation in the gate node of the driving TFT induced by clock-feed-through effect, reducing the leakage current that flows from the clock signal line to the power source line with a low voltage level. This reduction in the leakage current can improve the degradation in the voltage of the clock signal and thus avoid the increase in the rising time of the scan pulse. Measurements for extracting the drain current versus gate-to-source voltage (ID - VGS) curves of a fabricated a-Si:H TFT are made to establish a simulation TFT model by fitting the obtained curves. For the same parameters of the TFTs and capacitances, the leakage current and the rising time of the output waveform of the proposed circuit are 45.45% and 21.36% lower, respectively, than those of previously developed gate driver.
原文 | English |
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文章編號 | 9032101 |
頁(從 - 到) | 302-307 |
頁數 | 6 |
期刊 | IEEE Journal of the Electron Devices Society |
卷 | 8 |
DOIs | |
出版狀態 | Published - 2020 |
All Science Journal Classification (ASJC) codes
- 生物技術
- 電子、光磁材料
- 電氣與電子工程