Low-power and low-voltage fully parallel content-addressable memory

Chi Sheng Lin, Kuan Hua Chen, Bin-Da Liu

研究成果: Conference article

6 引文 (Scopus)

摘要

This paper presents a novel VLSI architecture for a fully parallel static type content addressable memory with low-power, low-voltage, and high-reliability features. In this paper, the proposed CAM word structure adopts static pseudo nMOS circuit that not only improves system reliability, but also prevents using clock signal to drive overall system. In order to reduce static power occurred in the proposed CAM word structure, a precomputation approach is used to turn off majority part of pseudo nMOS circuits. The whole design was simulated by HSPICE with the TSMC 0.35 μm SPQM CMOS process. With a 128 words by 30 bits CAM size, the simulation results indicate that the proposed circuit operates up to 250 MHz with the power-performance metric less than 59 fJ/bit/search.

原文English
期刊Proceedings - IEEE International Symposium on Circuits and Systems
5
出版狀態Published - 2003 七月 14
事件Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand
持續時間: 2003 五月 252003 五月 28

指紋

Associative storage
Computer aided manufacturing
Networks (circuits)
Electric potential
Clocks

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

引用此文

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abstract = "This paper presents a novel VLSI architecture for a fully parallel static type content addressable memory with low-power, low-voltage, and high-reliability features. In this paper, the proposed CAM word structure adopts static pseudo nMOS circuit that not only improves system reliability, but also prevents using clock signal to drive overall system. In order to reduce static power occurred in the proposed CAM word structure, a precomputation approach is used to turn off majority part of pseudo nMOS circuits. The whole design was simulated by HSPICE with the TSMC 0.35 μm SPQM CMOS process. With a 128 words by 30 bits CAM size, the simulation results indicate that the proposed circuit operates up to 250 MHz with the power-performance metric less than 59 fJ/bit/search.",
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Low-power and low-voltage fully parallel content-addressable memory. / Lin, Chi Sheng; Chen, Kuan Hua; Liu, Bin-Da.

於: Proceedings - IEEE International Symposium on Circuits and Systems, 卷 5, 14.07.2003.

研究成果: Conference article

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T1 - Low-power and low-voltage fully parallel content-addressable memory

AU - Lin, Chi Sheng

AU - Chen, Kuan Hua

AU - Liu, Bin-Da

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N2 - This paper presents a novel VLSI architecture for a fully parallel static type content addressable memory with low-power, low-voltage, and high-reliability features. In this paper, the proposed CAM word structure adopts static pseudo nMOS circuit that not only improves system reliability, but also prevents using clock signal to drive overall system. In order to reduce static power occurred in the proposed CAM word structure, a precomputation approach is used to turn off majority part of pseudo nMOS circuits. The whole design was simulated by HSPICE with the TSMC 0.35 μm SPQM CMOS process. With a 128 words by 30 bits CAM size, the simulation results indicate that the proposed circuit operates up to 250 MHz with the power-performance metric less than 59 fJ/bit/search.

AB - This paper presents a novel VLSI architecture for a fully parallel static type content addressable memory with low-power, low-voltage, and high-reliability features. In this paper, the proposed CAM word structure adopts static pseudo nMOS circuit that not only improves system reliability, but also prevents using clock signal to drive overall system. In order to reduce static power occurred in the proposed CAM word structure, a precomputation approach is used to turn off majority part of pseudo nMOS circuits. The whole design was simulated by HSPICE with the TSMC 0.35 μm SPQM CMOS process. With a 128 words by 30 bits CAM size, the simulation results indicate that the proposed circuit operates up to 250 MHz with the power-performance metric less than 59 fJ/bit/search.

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