Low-power and low-voltage fully parallel content-addressable memory

This paper presents a novel VLSI architecture for a fully parallel static type content addressable memory with low-power, low-voltage, and high-reliability features. In this paper, the proposed CAM word structure adopts static pseudo nMOS circuit that not only improves system reliability, but also prevents using clock signal to drive overall system. In order to reduce static power occurred in the proposed CAM word structure, a precomputation approach is used to turn off majority part of pseudo nMOS circuits. The whole design was simulated by HSPICE with the TSMC 0.35 μm SPQM CMOS process. With a 128 words by 30 bits CAM size, the simulation results indicate that the proposed circuit operates up to 250 MHz with the power-performance metric less than 59 fJ/bit/search.