Low-power and wide-bandwidth cyclic ADC with capacitor and opamp reuse techniques for CMOS image sensor application

Jin Fu Lin, Soon Jyh Chang, Chin Fong Chiu, Hann Huei Tsai, Jiann Jong Wang

研究成果: Article同行評審

16 引文 斯高帕斯(Scopus)

摘要

In this paper, a power-efficient programmable gain amplifier (PGA) and a cyclic analog-to-digital converter (ADC) are developed for a satellite CMOS image sensor system. The cyclic ADC employs capacitor and opamp reuse techniques to reduce power consumption and occupied silicon area. Moreover, a power-efficient and wide-bandwidth telescopic cascode gain boosting amplifier with capacitive level shifters is adopted to decrease its power consumption further. According to the system specification, a 10-bit, 14-MS/s cyclic ADC with the front-end PGA circuit is implemented in the TSMC 0.18-μm triple-well 1P3M CMOS image sensor (CIS) process. The proposed cyclic ADC achieves a spurious free dynamic range (SFDR) of 65.1 dB and a signal-to-noise distortion ratio (SNDR) of 52.44 dB with 5-MHz input frequency at 14 MS/s. The power consumption of the cyclic ADC and PGA from a 3.3 V supply are 15.84 mW and 5.78 mW, respectively. The total core area is 0.381 mm2.

原文English
文章編號05310989
頁(從 - 到)2044-2054
頁數11
期刊IEEE Sensors Journal
9
發行號12
DOIs
出版狀態Published - 2009

All Science Journal Classification (ASJC) codes

  • 儀器
  • 電氣與電子工程

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