Low-power design methodology for an on-chip bus with adaptive bandwidth capability

Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin

研究成果: Conference article同行評審

7 引文 斯高帕斯(Scopus)


This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achieves high data transmission rates while minimizing the number of repeaters by nearly 1/3. The technique uses low-impedance current-mode sensing to increase the data throughput and minimizes the static power dissipation inherent to current-mode signaling by adaptively changing the interconnection bandwidth given a change in input signal activity. Since bandwidth is related to power dissipation, the adaptive bus attains energy efficient data transmission by expending minimum power required to support the bus signal activity. The design method is based on statistical analysis of address streams extracted for typical benchmark programs using a microprocessor time-based simulator in combination with circuit-level power analysis. Simulation results indicate improvements in power dissipation of up to 65% and 40% over current and voltage mode signaling schemes, respectively.

頁(從 - 到)628-633
期刊Proceedings - Design Automation Conference
出版狀態Published - 2003
事件Proceedings of the 40th Design Automation Conference - Anaheim, CA, United States
持續時間: 2003 6月 22003 6月 6

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 控制與系統工程


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