A low power and high gain V-band CMOS low-noise amplifier (LNA) is proposed in this letter with a three-stage cascode topology. Using the gate-inductive gain-peaking technique to boost the gain, the proposed LNA achieves a good figure of merit (FOM) with less power consumption. This proposed LNA is fabricated in a 0.13 μm RF CMOS process, which achieves a peak gain of 21 dB at 53 GHz, a noise figure (NF) of 7.6 dB at 53 GHz, a 3 dB frequency bandwidth ranging from 51.3 to 55.8 GHz, an input 1 dB compression point (P 1 dB) of - 25 dBm at 53 GHz, and an input third-order intercept point (IIP3) of -16 dBm. Also, the LNA consumes only 15.1 mW at a supply voltage of 1.5 V. The calculated FOM is 0.81 in average. Such a V-band LNA design is applicable to the cost-efficiency integration of a microwave radiometer front-end circuit over the operation frequency band of 52 to 56 GHz.
All Science Journal Classification (ASJC) codes
- Condensed Matter Physics
- Electrical and Electronic Engineering