Low-power testing for C-testable iterative logic arrays

Shih Arn Hwang, Cheng Wen Wu

研究成果: Paper

1 引文 斯高帕斯(Scopus)

摘要

Deterministic test patterns often lead to much larger power consumption than normal input patterns, resulting in higher tester requirement and testing cost. We show that, without affecting the test quality, the most power-efficient test set for C-testable iterative logic arrays can be obtained. The proposed method takes only polynomial time with respect to the cell size, and is independent of the array size.

原文English
頁面355-358
頁數4
出版狀態Published - 1997 一月 1
事件Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China
持續時間: 1997 六月 31997 六月 5

Other

OtherProceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications
城市Taipei, China
期間97-06-0397-06-05

    指紋

All Science Journal Classification (ASJC) codes

  • Engineering(all)

引用此

Hwang, S. A., & Wu, C. W. (1997). Low-power testing for C-testable iterative logic arrays. 355-358. 論文發表於 Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications, Taipei, China, .