Deterministic test patterns often lead to much larger power consumption than normal input patterns, resulting in higher tester requirement and testing cost. We show that, without affecting the test quality, the most power-efficient test set for C-testable iterative logic arrays can be obtained. The proposed method takes only polynomial time with respect to the cell size, and is independent of the array size.
|出版狀態||Published - 1997 一月 1|
|事件||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications - Taipei, China|
持續時間: 1997 六月 3 → 1997 六月 5
|Other||Proceedings of the 1997 International Symposium on VLSI Technology, Systems, and Applications|
|期間||97-06-03 → 97-06-05|
All Science Journal Classification (ASJC) codes