Low-power VLSI architecture for the Viterbi decoder

Wann Shyang Ju, Ming Der Shieh, Ming Hwa Sheu

研究成果: Paper

2 引文 (Scopus)

摘要

This paper presents a VLSI architecture for the Viterbi decoder toward reducing average power dissipation based on the modified T-algorithm and the radix-2 butterfly module. Simulation results show that on the average, more than half of states at each time stage are not needed to be processed for the (4,1,6) convolutional code at bit error probability Pb≤10-2. Therefore, significant power reduction can be achieved by reducing the total number of path metric computations and eliminating waste memory read/write operations. Based on the TSMC 0.6 um SPDM process and the Compass cell library, the resulting core size is 2761*2996 um2.

原文English
頁面1201-1204
頁數4
出版狀態Published - 1997 十二月 1
事件Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2) - Sacramento, CA, USA
持續時間: 1997 八月 31997 八月 6

Other

OtherProceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2)
城市Sacramento, CA, USA
期間97-08-0397-08-06

指紋

Convolutional codes
Energy dissipation
Data storage equipment
Error probability

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

Ju, W. S., Shieh, M. D., & Sheu, M. H. (1997). Low-power VLSI architecture for the Viterbi decoder. 1201-1204. 論文發表於 Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, .
Ju, Wann Shyang ; Shieh, Ming Der ; Sheu, Ming Hwa. / Low-power VLSI architecture for the Viterbi decoder. 論文發表於 Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, .4 p.
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Ju, WS, Shieh, MD & Sheu, MH 1997, 'Low-power VLSI architecture for the Viterbi decoder', 論文發表於 Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, 97-08-03 - 97-08-06 頁 1201-1204.

Low-power VLSI architecture for the Viterbi decoder. / Ju, Wann Shyang; Shieh, Ming Der; Sheu, Ming Hwa.

1997. 1201-1204 論文發表於 Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, .

研究成果: Paper

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N2 - This paper presents a VLSI architecture for the Viterbi decoder toward reducing average power dissipation based on the modified T-algorithm and the radix-2 butterfly module. Simulation results show that on the average, more than half of states at each time stage are not needed to be processed for the (4,1,6) convolutional code at bit error probability Pb≤10-2. Therefore, significant power reduction can be achieved by reducing the total number of path metric computations and eliminating waste memory read/write operations. Based on the TSMC 0.6 um SPDM process and the Compass cell library, the resulting core size is 2761*2996 um2.

AB - This paper presents a VLSI architecture for the Viterbi decoder toward reducing average power dissipation based on the modified T-algorithm and the radix-2 butterfly module. Simulation results show that on the average, more than half of states at each time stage are not needed to be processed for the (4,1,6) convolutional code at bit error probability Pb≤10-2. Therefore, significant power reduction can be achieved by reducing the total number of path metric computations and eliminating waste memory read/write operations. Based on the TSMC 0.6 um SPDM process and the Compass cell library, the resulting core size is 2761*2996 um2.

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Ju WS, Shieh MD, Sheu MH. Low-power VLSI architecture for the Viterbi decoder. 1997. 論文發表於 Proceedings of the 1997 40th Midwest Symposium on Circuits and Systems. Part 1 (of 2), Sacramento, CA, USA, .