摘要
The phenomena and mechanisms of hot-carrier-induced threshold-voltage (V T ) shift in high-voltage p-type laterally diffused MOS (LDMOS) transistors are investigated. At low-|V gs| (absolute value of gate voltage) stress condition, electrons are injected and trapped in the gate oxide at the channel region near the drain, resulting in V T increase (Δ|V T| < 0). At high-|V gs| stress condition, however, severe VT decrease (Δ|VT
原文 | English |
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文章編號 | 5280275 |
頁(從 - 到) | 3203-3206 |
頁數 | 4 |
期刊 | IEEE Transactions on Electron Devices |
卷 | 56 |
發行號 | 12 |
DOIs | |
出版狀態 | Published - 2009 12月 1 |
All Science Journal Classification (ASJC) codes
- 電子、光磁材料
- 電氣與電子工程