Memory repair by die stacking with through silicon vias

Yung Fa Chou, Ding Ming Kwai, Cheng Wen Wu

研究成果: Conference contribution

11 引文 斯高帕斯(Scopus)

摘要

As we adopt more advanced process technologies, the volume production of memory devices, such as DRAM and Flash, becomes more difficult. It seems inevitable that during the ramp-up period, the initial manufacturing yield will be lower, and it takes more time and effort to improve the yield to a reasonable level. Although redundancy can be used to improve the yield eventually, the reserved spares may not be enough at the beginning, so most dies may be irreparable. We propose the usage of three-dimensional (3D) integration to achieve yield enhancement. Through silicon vias (TSVs) patch good memory blocks in a bad die with those in another bad die by bonding them together and enabling the built-in circuit. The die stack has the same functionality, though slightly increases delay and power. Nevertheless, if the production yield takes a long time to achieve, the 3D patched memory is deemed to be a transitional-period product. It does help to shorten time-to-market and make the irreparable memories profitable.

原文English
主出版物標題Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
頁面53-58
頁數6
DOIs
出版狀態Published - 2009 十二月 25
事件2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009 - Hsinchu, Taiwan
持續時間: 2009 八月 312009 九月 2

出版系列

名字Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Conference

Conference2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009
國家/地區Taiwan
城市Hsinchu
期間09-08-3109-09-02

All Science Journal Classification (ASJC) codes

  • 計算機理論與數學
  • 電腦科學應用
  • 硬體和架構
  • 電氣與電子工程

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