Mitigating BTI-induced degradation in STT-MRAM sensing schemes

Ing-Chao Lin, Yun Kae Law, Yuan Xie

研究成果: Article

4 引文 (Scopus)

摘要

Spin-transfer torque magnetic RAM (STT-MRAM), which uses a magnetic tunnel junction to store binary data, is a promising memory technology. With many benefits, such as low leakage power, high density, high endurance, and nonvolatility, it has been explored as an SRAM replacement for cache design or a DRAM replacement for main memory. Meanwhile, along with the continuous shrinking of CMOS process technology, the bias temperature instability (BTI) effect has become a major reliability issue. Prior work has investigated the influence of the BTI effect on the SRAM sense amplifier, but no investigation has been done for the STT-MRAM sense amplifier. Therefore, this paper investigates the BTI effect on STT-MRAM sense amplifiers. We propose a majority-based technique and an alternative sensing technique to reduce circuit degradation. To further improve sensing delay, we propose using forward body bias (FBB) on an access transistor with a positive voltage. Extensive simulation results are done to show the effectiveness of the proposed techniques. The sensing delay for reading zeros and ones can be reduced by 10.61% and 4.35%, respectively, on average, with the majority-based technique. The sensing delay for reading zeros and ones can be reduced by 4.42% and 1.83%, respectively, on average, using the alternative sensing technique. The sensing delay for reading zeros and ones can be reduced by 15.37% and 6.25%, respectively, on average, by using both techniques simultaneously. When using the majority-based and alternative sensing techniques with the FBB technique, the sensing delay for reading zeros and ones can be improved by 29.93% and 57.67%, respectively, on average. We also analyze the BTI-induced degradation of a high-performance sense amplifier and a low power sense amplifier with the proposed techniques. The simulation results show that our proposed technique and simulation flow can be easily extended to other sense amplifiers.

原文English
頁(從 - 到)50-62
頁數13
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
26
發行號1
DOIs
出版狀態Published - 2018 一月 1

指紋

Random access storage
Torque
Degradation
Static random access storage
Data storage equipment
Temperature
Tunnel junctions
Dynamic random access storage
Flow simulation
Transistors
Durability
Networks (circuits)
Electric potential

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

引用此文

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title = "Mitigating BTI-induced degradation in STT-MRAM sensing schemes",
abstract = "Spin-transfer torque magnetic RAM (STT-MRAM), which uses a magnetic tunnel junction to store binary data, is a promising memory technology. With many benefits, such as low leakage power, high density, high endurance, and nonvolatility, it has been explored as an SRAM replacement for cache design or a DRAM replacement for main memory. Meanwhile, along with the continuous shrinking of CMOS process technology, the bias temperature instability (BTI) effect has become a major reliability issue. Prior work has investigated the influence of the BTI effect on the SRAM sense amplifier, but no investigation has been done for the STT-MRAM sense amplifier. Therefore, this paper investigates the BTI effect on STT-MRAM sense amplifiers. We propose a majority-based technique and an alternative sensing technique to reduce circuit degradation. To further improve sensing delay, we propose using forward body bias (FBB) on an access transistor with a positive voltage. Extensive simulation results are done to show the effectiveness of the proposed techniques. The sensing delay for reading zeros and ones can be reduced by 10.61{\%} and 4.35{\%}, respectively, on average, with the majority-based technique. The sensing delay for reading zeros and ones can be reduced by 4.42{\%} and 1.83{\%}, respectively, on average, using the alternative sensing technique. The sensing delay for reading zeros and ones can be reduced by 15.37{\%} and 6.25{\%}, respectively, on average, by using both techniques simultaneously. When using the majority-based and alternative sensing techniques with the FBB technique, the sensing delay for reading zeros and ones can be improved by 29.93{\%} and 57.67{\%}, respectively, on average. We also analyze the BTI-induced degradation of a high-performance sense amplifier and a low power sense amplifier with the proposed techniques. The simulation results show that our proposed technique and simulation flow can be easily extended to other sense amplifiers.",
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Mitigating BTI-induced degradation in STT-MRAM sensing schemes. / Lin, Ing-Chao; Law, Yun Kae; Xie, Yuan.

於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 卷 26, 編號 1, 01.01.2018, p. 50-62.

研究成果: Article

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