In this paper, a mixed-level design methodology for digitally controlled power converter IC is proposed. The proposed design methodology can reduce time for debugging and accelerate design period for digitally controlled power converter IC designers. With proper mixing of behavioral model, register-transfer level (RTL) model and transistor level model, the simulation can be more time effective without losing accuracy. The proposed design methodology is demonstrated with digital control voltage mode buck converter IC and the chip was manufactured by TSMC 0.18-mu textbfm CMOS process. The measurement results shows the consistent with simulation results. In addition, simulation time is much less than traditional design methodology.