@inproceedings{e6c1cb8b26e242fa9fa84c0f503d109a,
title = "Mixed-Level Design Methodology With SystemVerilog Behavior Models for Digitally Controlled Power Converter ICs",
abstract = "SystemVerilog behavior models of power converter integrated circuits for mixed-level design methodology was proposed. When SystemVerilog is used to establish behavior models for circuits, the process of transistor-level design can be omitted to prevent prolonging the redesign time. Moreover, models created in this manner can sustain simulation accuracy while reducing the simulation time by 57% compared with models conventionally created using Verilog-AMS. In this study, 0.18-μm CMOS fabrication was used to verify the effectiveness of the proposed SystemVerilog model and mixed-level design in the creation of a digitally controlled buck converter integrated circuit.",
author = "Yeh, {Wei Ting} and Chang, {Chung Lun} and Yin, {Shang Chih} and Tsai, {Chien Hung}",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 12th IEEE Global Conference on Consumer Electronics, GCCE 2023 ; Conference date: 10-10-2023 Through 13-10-2023",
year = "2023",
doi = "10.1109/GCCE59613.2023.10315270",
language = "English",
series = "GCCE 2023 - 2023 IEEE 12th Global Conference on Consumer Electronics",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1172--1175",
booktitle = "GCCE 2023 - 2023 IEEE 12th Global Conference on Consumer Electronics",
address = "United States",
}