In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.
|出版狀態||Published - 2011 十二月 1|
|事件||2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011 - Shanghai, China|
持續時間: 2011 十一月 7 → 2011 十一月 9
|Other||2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011|
|期間||11-11-07 → 11-11-09|
All Science Journal Classification (ASJC) codes