Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

S. Venugopalan; Y. S. Chauhan; Darsen Lu; M. A. Karim; Ali M. Niknejad; Chenming Hu

doi:10.1109/NVMTS.2011.6137100

Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

S. Venugopalan, Y. S. Chauhan, Darsen Lu, M. A. Karim, Ali M. Niknejad, Chenming Hu

研究成果: Paper › 同行評審

2 引文斯高帕斯（Scopus）

摘要

In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

原文	English
頁面	125-128
頁數	4
DOIs	https://doi.org/10.1109/NVMTS.2011.6137100
出版狀態	Published - 2011 12月 1
事件	2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011 - Shanghai, China 持續時間: 2011 11月 7 → 2011 11月 9

Other

Other	2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011
國家/地區	China
城市	Shanghai
期間	11-11-07 → 11-11-09

All Science Journal Classification (ASJC) codes

硬體和架構

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10.1109/NVMTS.2011.6137100

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doi = "10.1109/NVMTS.2011.6137100",

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AU - Venugopalan, S.

AU - Chauhan, Y. S.

AU - Lu, Darsen

AU - Karim, M. A.

AU - Niknejad, Ali M.

AU - Hu, Chenming

PY - 2011/12/1

Y1 - 2011/12/1

N2 - In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

AB - In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

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Y2 - 7 November 2011 through 9 November 2011

ER -

Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

摘要

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