Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations

S. Venugopalan, Y. S. Chauhan, Darsen Lu, M. A. Karim, Ali M. Niknejad, Chenming Hu

研究成果: Paper同行評審

2 引文 斯高帕斯(Scopus)

摘要

In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.

原文English
頁面125-128
頁數4
DOIs
出版狀態Published - 2011 十二月 1
事件2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011 - Shanghai, China
持續時間: 2011 十一月 72011 十一月 9

Other

Other2011 11th Annual Non-Volatile Memory Technology Symposium, NVMTS 2011
國家/地區China
城市Shanghai
期間11-11-0711-11-09

All Science Journal Classification (ASJC) codes

  • 硬體和架構

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