Modeling of Bilayer Modulated RRAM and Its Array Performance for Compute-in-Memory Applications

Jia Wei Lee, Tzu Chin Chou, Po An Chen, Meng Hsueh Chiang

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

This article presents a modified compact model of resistive random access memory (RRAM) with a tunneling barrier. The bilayer modulated RRAM can be integrated into a higher density array, reducing leakage current in standby mode. The model demonstrates current transition behavior from low- to high-bias regions by considering both bulk-limited and electrode-limited transport mechanisms. This model can evaluate RRAM array performance under various pulsing conditions and device parameter variations with calibrated model cards. The compute-in-memory application requires precise current sum results hindered by the wire resistance loading effect. This study also evaluates various sizes of arrays suitable for performance improvement.

原文English
頁(從 - 到)151-158
頁數8
期刊IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
9
發行號2
DOIs
出版狀態Published - 2023 12月 1

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 硬體和架構
  • 電氣與電子工程

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