Modeling of RRAM with Embedded Tunneling Barrier and Its Application in Logic in Memory

Jia Wei Lee, Meng Hsueh Chiang

研究成果: Article同行評審

摘要

This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided so as to optimize programming efficiency for logic-in-memory application.

原文English
文章編號9137335
頁(從 - 到)1390-1396
頁數7
期刊IEEE Journal of the Electron Devices Society
8
DOIs
出版狀態Published - 2020

All Science Journal Classification (ASJC) codes

  • Biotechnology
  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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