TY - JOUR
T1 - Modified polycrystalline silicon chemical-vapor deposition process for improving roughness at oxide/polycrystalline silicon interface
AU - Chang, J. J.
AU - Hsieh, I. E.
AU - Wang, Y. L.
AU - Tseng, W. T.
AU - Liu, C. P.
AU - Lan, C. Y.
PY - 2005/1/24
Y1 - 2005/1/24
N2 - A new modified low pressure chemical-vapor deposition process for stacked polysilicon (poly-Si) films is developed in this study. The proposed stacked film process combines polysilicon with amorphous silicon films. In this process, polysilicon film was deposited first at 630° C, followed by a continuous temperature decrease down to 560°C for the deposition of amorphous silicon film. It was found that the doped stacked polysilicon films deposited by this process result in lowering of surface roughness, together with reduction of the (311) phase of the doped amorphous silicon and (110) phase of the doped polysilicon. As a consequence, device performance based on the stacked films also improves. Results of surface roughness analysis indicated that the doped stacked polysilicon film has a root-mean square surface roughness (Rrms) of 78 Å, which is smaller than those of doped conventional (630 °C) polysilicon film (Rrms=97 Å), and doped amorphous silicon film (Rrms=123 Å, deposited at 560°C). Transmission electron microscopic (TEM) observation performed at oxide/polysilicon interface showed that the conventional (630°C) oxide/polysilicon interface has high angle grain boundaries on the polysilicon side, which may induce leakage current around the interfacial area.
AB - A new modified low pressure chemical-vapor deposition process for stacked polysilicon (poly-Si) films is developed in this study. The proposed stacked film process combines polysilicon with amorphous silicon films. In this process, polysilicon film was deposited first at 630° C, followed by a continuous temperature decrease down to 560°C for the deposition of amorphous silicon film. It was found that the doped stacked polysilicon films deposited by this process result in lowering of surface roughness, together with reduction of the (311) phase of the doped amorphous silicon and (110) phase of the doped polysilicon. As a consequence, device performance based on the stacked films also improves. Results of surface roughness analysis indicated that the doped stacked polysilicon film has a root-mean square surface roughness (Rrms) of 78 Å, which is smaller than those of doped conventional (630 °C) polysilicon film (Rrms=97 Å), and doped amorphous silicon film (Rrms=123 Å, deposited at 560°C). Transmission electron microscopic (TEM) observation performed at oxide/polysilicon interface showed that the conventional (630°C) oxide/polysilicon interface has high angle grain boundaries on the polysilicon side, which may induce leakage current around the interfacial area.
UR - http://www.scopus.com/inward/record.url?scp=9944257986&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=9944257986&partnerID=8YFLogxK
U2 - 10.1016/j.tsf.2004.06.165
DO - 10.1016/j.tsf.2004.06.165
M3 - Article
AN - SCOPUS:9944257986
SN - 0040-6090
VL - 472
SP - 164
EP - 168
JO - Thin Solid Films
JF - Thin Solid Films
IS - 1-2
ER -