TY - JOUR
T1 - Modular design of high-efficiency hardware median filter architecture
AU - Lin, Shih Hsiang
AU - Chen, Pei Yin
AU - Hsu, Chih Kun
N1 - Funding Information:
Manuscript received May 22, 2017; revised September 30, 2017 and October 30, 2017; accepted October 31, 2017. Date of publication November 21, 2017; date of current version May 8, 2018. This work was supported in part by the NOVATEK Fellowship and in part by the Ministry of Science and Technology of Taiwan under Grant MOST 105-2221-E-006-157-MY3. This paper was recommended by Associate Editor G. Masera. (Corresponding author: Pei-Yin Chen.) The authors are with the Digital IC Design Laboratory, Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan 70101, Taiwan (e-mail: [email protected]; pychen@ mail.ncku.edu.tw; [email protected]).
Publisher Copyright:
© 2004-2012 IEEE.
PY - 2018/6
Y1 - 2018/6
N2 - This paper presents the hardware design and implementation of 1-D median filter that uses modular architecture, which produces median results hierarchically. Different types of submodules could be applied to form a customized architecture in order to meet different constraints and requirements. Complete analysis and hardware-oriented optimization were performed to achieve the optimal configurations when the input size and data length were changed. As the data length increases, the required resources and latency increase linearly, while the maximal operation frequency is nearly independent to data length. When our filter is synthesized using 90-nm process technology, its operating frequency could achieve more than 2000 MHz and resource consumption is reduced by 23.29% when compared with the state-of-the-art design. The experimental results show that the proposed cascaded architecture is superior to existing designs in terms of maximal operating speed and resource costs.
AB - This paper presents the hardware design and implementation of 1-D median filter that uses modular architecture, which produces median results hierarchically. Different types of submodules could be applied to form a customized architecture in order to meet different constraints and requirements. Complete analysis and hardware-oriented optimization were performed to achieve the optimal configurations when the input size and data length were changed. As the data length increases, the required resources and latency increase linearly, while the maximal operation frequency is nearly independent to data length. When our filter is synthesized using 90-nm process technology, its operating frequency could achieve more than 2000 MHz and resource consumption is reduced by 23.29% when compared with the state-of-the-art design. The experimental results show that the proposed cascaded architecture is superior to existing designs in terms of maximal operating speed and resource costs.
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U2 - 10.1109/TCSI.2017.2770216
DO - 10.1109/TCSI.2017.2770216
M3 - Article
AN - SCOPUS:85035794836
SN - 1549-8328
VL - 65
SP - 1929
EP - 1940
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 6
ER -