Modular design of high-efficiency hardware median filter architecture

Shih Hsiang Lin, Pei Yin Chen, Chih Kun Hsu

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

This paper presents the hardware design and implementation of 1-D median filter that uses modular architecture, which produces median results hierarchically. Different types of submodules could be applied to form a customized architecture in order to meet different constraints and requirements. Complete analysis and hardware-oriented optimization were performed to achieve the optimal configurations when the input size and data length were changed. As the data length increases, the required resources and latency increase linearly, while the maximal operation frequency is nearly independent to data length. When our filter is synthesized using 90-nm process technology, its operating frequency could achieve more than 2000 MHz and resource consumption is reduced by 23.29% when compared with the state-of-the-art design. The experimental results show that the proposed cascaded architecture is superior to existing designs in terms of maximal operating speed and resource costs.

原文English
頁(從 - 到)1929-1940
頁數12
期刊IEEE Transactions on Circuits and Systems I: Regular Papers
65
發行號6
DOIs
出版狀態Published - 2018 6月

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

指紋

深入研究「Modular design of high-efficiency hardware median filter architecture」主題。共同形成了獨特的指紋。

引用此