Module placement with boundary constraints using B*-trees

J. M. Lin, H. E. Yi, Y. W. Chang

研究成果: Article同行評審

18 引文 斯高帕斯(Scopus)

摘要

The module placement problem is to determine the co-ordinates of logic modules in a chip such that no two modules overlap and some cost (e.g. silicon area, interconnection length, etc.) is optimised. To shorten connections between inputs and outputs and/or make related modules adjacent, it is desired to place some modules along the specific boundaries of a chip. To deal with such boundary constraints, we explore the feasibility conditions of a B*-tree with boundary constraints and develop a simulated annealing-based algorithm using B*-trees. Unlike most previous work, the proposed algorithm guarantees a feasible B*-tree with boundary constraints for each perturbation. Experimental results show that the algorithm can obtain a smaller silicon area than the most recent work based on sequence pairs.

原文English
頁(從 - 到)251-256
頁數6
期刊IEE Proceedings: Circuits, Devices and Systems
149
發行號4
DOIs
出版狀態Published - 2002 八月

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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