@inproceedings{f91b1fa319a244d5a2e1c8f0f5eca72a,
title = "MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization",
abstract = "Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.",
author = "Lin, {W. C.} and Huang, {H. P.} and Kao, {K. H.} and Chiang, {M. H.} and D. Lu and Hsu, {W. C.} and Wang, {Y. H.} and Ma, {W. C.Y.} and Tsai, {H. H.} and Lee, {Y. J.} and Chiang, {H. L.} and Wang, {J. F.} and I. Radu",
note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023 ; Conference date: 11-09-2023 Through 14-09-2023",
year = "2023",
doi = "10.1109/ESSDERC59256.2023.10268514",
language = "English",
series = "European Solid-State Device Research Conference",
publisher = "Editions Frontieres",
pages = "9--12",
booktitle = "ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference",
}