MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization

W. C. Lin, H. P. Huang, K. H. Kao, M. H. Chiang, D. Lu, W. C. Hsu, Y. H. Wang, W. C.Y. Ma, H. H. Tsai, Y. J. Lee, H. L. Chiang, J. F. Wang, I. Radu

研究成果: Conference contribution

摘要

Power consumption of MOSFETs leading to undesired heat has become one of the major challenges of CMOS working at cryogenic temperatures for novel applications. Although lowering temperature (T) may benefit supply voltage (VDD) scaling and power reduction, it is still unclear how the correlations between VDD and T impact the device performance and power efficiency. In this work, we present a comprehensive study on the power performance evaluation, based on the characterization of MOSFETs at different VDD within a temperature range from 300 to 10 K. Owing to the saturation of subthreshold swing, limited VDD scaling with optimal VDD(T) at T ≦ 100 K is the key to acquire higher gate overdrive voltage for the performance improvement in cryogenic conditions.

原文English
主出版物標題ESSDERC 2023 - IEEE 53rd European Solid-State Device Research Conference
發行者Editions Frontieres
頁面9-12
頁數4
ISBN(電子)9798350304237
DOIs
出版狀態Published - 2023
事件53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023 - Lisbon, Portugal
持續時間: 2023 9月 112023 9月 14

出版系列

名字European Solid-State Device Research Conference
2023-September
ISSN(列印)1930-8876

Conference

Conference53rd IEEE European Solid-State Device Research Conference, ESSDERC 2023
國家/地區Portugal
城市Lisbon
期間23-09-1123-09-14

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 安全、風險、可靠性和品質

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