Multi-Project System-on-Chip (MP-SoC): A novel test vehicle for SoC silicon prototyping

Chun Ming Huang, Kuen Jong Lee, Chih Chyau Yang, Wen Hsiang Hu, Shi Shen Wang, Jeng Bin Chen, Chi Shi Chen, Lan Da Van, Chien Ming Wu, Wei Chang Tsai, Jing Yang Jou

研究成果: Conference contribution

12 引文 斯高帕斯(Scopus)


In this paper, we propose a novel SoC design methodology referred to as Multi-Project System-on-a-Chip (MP-SoC), which can integrate multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced due to the sharing of a common SoC platform. The design flows for the system architecture, individual IP blocks, as well as the logic and physical implementations of MP-SoC are explored. The isolation mechanism to prevent interference among the IPs and the arbitration mechanism to grant the bus usage for master IPs are also presented. A test chip named MP-SoC-I that includes 8 SoC projects from 4 universities was selected as a demonstration example for verifying the MP-SoC design concept. This chip is designed and implemented in TSMC 0.13μm CMOS generic logic process technology, and the total silicon area for MP-SoC-I test chip is 4950μm×4938μm. Experimental results of MP-SoC-I test chip show that all projects are successfully implemented in the common platform and 82.91% silicon area is saved with this MP-SoC methodology as compared with the case where multiple SoC projects are fabricated individually.

主出版物標題2006 IEEE International Systems-on-Chip Conference, SOC
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(列印)0780397819, 9780780397811
出版狀態Published - 2006 一月 1
事件2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States
持續時間: 2006 九月 242006 九月 27


名字2006 IEEE International Systems-on-Chip Conference, SOC


Other2006 IEEE International Systems-on-Chip Conference, SOC
國家United States
城市Austin, TX

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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