Multi-Project System-on-Chip (MP-SoC): A novel test vehicle for SoC silicon prototyping

In this paper, we propose a novel SoC design methodology referred to as Multi-Project System-on-a-Chip (MP-SoC), which can integrate multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced due to the sharing of a common SoC platform. The design flows for the system architecture, individual IP blocks, as well as the logic and physical implementations of MP-SoC are explored. The isolation mechanism to prevent interference among the IPs and the arbitration mechanism to grant the bus usage for master IPs are also presented. A test chip named MP-SoC-I that includes 8 SoC projects from 4 universities was selected as a demonstration example for verifying the MP-SoC design concept. This chip is designed and implemented in TSMC 0.13μm CMOS generic logic process technology, and the total silicon area for MP-SoC-I test chip is 4950μm×4938μm. Experimental results of MP-SoC-I test chip show that all projects are successfully implemented in the common platform and 82.91% silicon area is saved with this MP-SoC methodology as compared with the case where multiple SoC projects are fabricated individually.