Nano-scaled Ge FinFETs with low temperature ferroelectric HfZrOx on specific interfacial layers exhibiting 65% S.S. reduction and improved ION

C. J. Su, Y. T. Tang, Y. C. Tsou, P. J. Sung, F. J. Hou, C. J. Wang, S. T. Chung, C. Y. Hsieh, Y. S. Yeh, F. K. Hsueh, K. H. Kao, S. S. Chuang, C. T. Wu, T. Y. You, Y. L. Jian, T. H. Chou, Y. L. Shen, B. Y. Chen, G. L. Luo, T. C. HongK. P. Huang, M. C. Chen, Y. J. Lee, T. S. Chao, T. Y. Tseng, W. F. Wu, G. W. Huang, J. M. Shieh, W. K. Yeh, Y. H. Wang

研究成果: Conference contribution

19 引文 斯高帕斯(Scopus)

摘要

Ge n- and p-FinFETs with different interfacial layer ferroelectric HfZrOx (IL-FE-HZO) gate stacks have been demonstrated systematically by various annealing conditions for the first time. Microwave annealing (MWA) not only shows enhanced FE characteristics but also suppresses the gate leakage and Ge interdiffusion compared with conventional rapid thermal annealing (RTA). While HZO on Al2O3 IL results in paraelectric behavior, HZO on GeOx IL exhibits significant FE. High Ion/Ioff (> 107) and low subthreshold slope (S.S. ∼ 58 mV/dec.) are demonstrated by a Ge nFinFET with a gate length (Lg) of 60 nm and a FE-HZO/GeOx gate stack.

原文English
主出版物標題2017 Symposium on VLSI Technology, VLSI Technology 2017
發行者Institute of Electrical and Electronics Engineers Inc.
頁面T152-T153
ISBN(電子)9784863486058
DOIs
出版狀態Published - 2017 七月 31
事件37th Symposium on VLSI Technology, VLSI Technology 2017 - Kyoto, Japan
持續時間: 2017 六月 52017 六月 8

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
ISSN(列印)0743-1562

Other

Other37th Symposium on VLSI Technology, VLSI Technology 2017
國家Japan
城市Kyoto
期間17-06-0517-06-08

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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