Nanosheet-Compatible Complementary-Field Effect Transistor Logic Non-Volatile Memory Device

Shu Wei Chang, Yu Ming Chang, Wen Hsi Lee, Yao Jen Lee, Darsen D. Lu

研究成果: Article同行評審

摘要

This study proposes a logic non-volatile memory (NVM) device based on the state-of-the-art gate-all-around (GAA) nanosheet process. By adopting a complementary FET structure, we not only reduce the layout footprint area but also demonstrate the compatibility with sub-3nm nanosheet CMOS technology. We simulated the device in TCAD for program and erase operations, considering both Fowler Nordheim tunneling and hot carrier injection mechanisms. The memory window is optimized by adjusting the device structure, such as tunneling and blocking oxide thicknesses, top- and bottom-channel width, and the floating gate length, resulting in a significant enhancement in the memory window. Finally, NAND/NOR type CFET logic NVM are demonstrated to reveal the possible applications of gate-all-around stacked junctionless nanosheet transistor towards embedded flash.

原文English
文章編號095003
期刊ECS Journal of Solid State Science and Technology
11
發行號9
DOIs
出版狀態Published - 2022 9月

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料

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