Near-Optimal Scheduling for IC Packaging Operations Considering Processing-Time Variations and Factory Practices

Due to the short life cycles of electronic products, trial run lots of new products are crucial in IC packaging for production verification and engineering adjustments. The processing time of trial run lots may differ significantly from production lots due to engineering adjustments and is difficult to predict without sufficient historical data. The purpose of this letter is to develop a framework for near-optimal scheduling of IC packaging considering processing time variations and factory practices. Using an orthogonal greedy algorithm and recurrent neural network, this framework extracts key features and predicts the processing times of trial run lots and production lots for each operation using these algorithms. After formulating the scheduling problem in an integer linear programming form, an ordinal optimization method is embedded within the decomposition and coordination framework to obtain dynamic and near-optimal schedules in a computationally efficient manner. This approach can improve the efficiency of IC packaging and potentially other operations by optimizing lot scheduling, reducing production tardiness, and increasing productivity in the factory, paving the way for self-optimizing factories in the future.