In this paper, we propose a Network Virtual Platform (NetVP) to develop and verify network accelerator like an IPsec processor. The NetVP provides on-line verification mechanism and is suitable for ESL top-down design flow, supporting developments of un-timed as well as timed models. System development using this NetVP is efficient and flexible since it allows the designer to explore design spaces such as the network bandwidth and system architecture easily.
|出版狀態||Published - 2012 9月 28|
|事件||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of|
持續時間: 2012 5月 20 → 2012 5月 23
|Other||2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012|
|國家/地區||Korea, Republic of|
|期間||12-05-20 → 12-05-23|
All Science Journal Classification (ASJC) codes