NetVP: A system-level NETwork Virtual Platform for network accelerator development

Chen Chieh Wang, Sheng Hsin Lo, Yao Ning Liu, Chung-Ho Chen

研究成果: Paper

1 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose a Network Virtual Platform (NetVP) to develop and verify network accelerator like an IPsec processor. The NetVP provides on-line verification mechanism and is suitable for ESL top-down design flow, supporting developments of un-timed as well as timed models. System development using this NetVP is efficient and flexible since it allows the designer to explore design spaces such as the network bandwidth and system architecture easily.

原文English
頁面249-252
頁數4
DOIs
出版狀態Published - 2012 九月 28
事件2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
持續時間: 2012 五月 202012 五月 23

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家Korea, Republic of
城市Seoul
期間12-05-2012-05-23

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

指紋 深入研究「NetVP: A system-level NETwork Virtual Platform for network accelerator development」主題。共同形成了獨特的指紋。

  • 引用此

    Wang, C. C., Lo, S. H., Liu, Y. N., & Chen, C-H. (2012). NetVP: A system-level NETwork Virtual Platform for network accelerator development. 249-252. 論文發表於 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of. https://doi.org/10.1109/ISCAS.2012.6271806