New architecture for fast modular multiplication

Yeong Jiunn Juang, Erl Huei Lu, Jau Yien Lee, Chin Hsing Chen

研究成果: Paper同行評審

3 引文 斯高帕斯(Scopus)

摘要

An algorithm for computing AB mod N is developed, where N can be any positive integer. Since a carry-save adder can be used to implement the algorithm, a VLSI (very-large-scale integration) multiplier with area O(n) for multiplying n-bit integers is very fast. It is shown that n-bit AB mod N operation with 2n-1 ≤ N < 2n requires n short-period cycles and at most six long-period cycles. The period of the short cycles is independent of the size of the multiplier, and the long period is equal to the n-bit full-adder propagation delay time. If N is not in the interval 2n-1 ≤ N < 2n, the VLSI circuit needs more than six long-period cycles. The parallel adder can be replaced by a carry-lookahead adder to improve the speed. The multiplier was designed, and no error was found in its logic simulation. The architecture of the multiplier has regular, modular and expansible features and is therefore suitable for VLSI implementation.

原文English
頁面357-360
頁數4
出版狀態Published - 1989 十二月 1
事件International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan
持續時間: 1989 五月 171989 五月 19

Other

OtherInternational Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers
城市Taipei, Taiwan
期間89-05-1789-05-19

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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