New representation for programmable logic arrays to facilitate testing and logic design

Jing Jou Tang, Kuen-Jong Lee, Bin-Da Liu

研究成果: Conference contribution

1 引文 斯高帕斯(Scopus)

摘要

In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). Through this graph model, most realistic PLA faults, including crosspoint, stuck-at, break and bridging faults, can be modeled. The work of diagnosis and test generation is thus simplified. Also many logic design problems such as folding, minimization and decomposition can be done using this representation.

原文English
主出版物標題Proceedings of the 10th IEEE Region Conference on Computer, Communication, Control and Power Engineering
發行者Publ by IEEE
頁面561-564
頁數4
ISBN(列印)0780312333
出版狀態Published - 1993
事件Proceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5) - Beijing, China
持續時間: 1993 十月 191993 十月 21

Other

OtherProceedings of the 1993 IEEE Region 10 Conference on Computer, Communication, Control and Power Engineering (TENCON '93). Part 1 (of 5)
城市Beijing, China
期間93-10-1993-10-21

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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