NEW THREE-LAYER DETAILED ROUTER FOR VLSI LAYOUT.

Jer Min Jou, Jau Yien Lee, Jhing Fa Wang

研究成果: Conference contribution

4 引文 斯高帕斯(Scopus)

摘要

A three-layer detailed router that is capable of routing a rectilinear wiring area containing obstacles such as prerouted pins is presented. It supports pins fixed on all sides of the area. A routing methodology is developed; it is basically a divide-and-conquer that partitions the routing area into subones by specially chosen cut lines and then uses a concurrently bidirectional column scanning approach to route each subregion. In each column, a signal column maze router with backtracking is developed. This router consistently outperforms several known routers in quality of wiring.

原文English
主出版物標題Unknown Host Publication Title
發行者IEEE
頁面382-385
頁數4
ISBN(列印)0818608145
出版狀態Published - 1987 十二月 1

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • 引用此

    Jou, J. M., Lee, J. Y., & Wang, J. F. (1987). NEW THREE-LAYER DETAILED ROUTER FOR VLSI LAYOUT.Unknown Host Publication Title (頁 382-385). IEEE.