Novel high-density low-power high-performance double-gate logic techniques

Meng Hsueh Chiang, Keunwoo Kim, Christophe Tretz, Ching Te Chuang

研究成果: Conference article同行評審

16 引文 斯高帕斯(Scopus)

摘要

Double-gate logic circuit schemes were developed using symmetrical gates for NOR, NAND, and pass gates, in order to reduce the area of the leakage/ active power. The performance improvement and the power reduction for NAND, NOR, and pass gates were studied via the two dimensional numeric device simulator, called MEDICI. It was found that since symmetrical double-gate devices have two identical channels near the front and the back surfaces, the number of transistors required to implement a given logic function could be reduced when the two gates were operated independently. The power/performance advantages were evaluated and demonstrated using the two dimensional numerical device simulator to directly simulate the circuit structures.

原文English
頁(從 - 到)122-123
頁數2
期刊Proceedings - IEEE International SOI Conference
出版狀態Published - 2004 12月 1
事件2004 IEEE International SOI Conference, Proceedings - Charleston, SC, United States
持續時間: 2004 10月 42004 10月 7

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 電氣與電子工程

指紋

深入研究「Novel high-density low-power high-performance double-gate logic techniques」主題。共同形成了獨特的指紋。

引用此