Double-gate logic circuit schemes were developed using symmetrical gates for NOR, NAND, and pass gates, in order to reduce the area of the leakage/ active power. The performance improvement and the power reduction for NAND, NOR, and pass gates were studied via the two dimensional numeric device simulator, called MEDICI. It was found that since symmetrical double-gate devices have two identical channels near the front and the back surfaces, the number of transistors required to implement a given logic function could be reduced when the two gates were operated independently. The power/performance advantages were evaluated and demonstrated using the two dimensional numerical device simulator to directly simulate the circuit structures.
|頁（從 - 到）||122-123|
|期刊||Proceedings - IEEE International SOI Conference|
|出版狀態||Published - 2004 12月 1|
|事件||2004 IEEE International SOI Conference, Proceedings - Charleston, SC, United States|
持續時間: 2004 10月 4 → 2004 10月 7
All Science Journal Classification (ASJC) codes