Novel strategies of FSG - CMP for within-wafer uniformity improvement and wafer edge yield enhancement beyond 0.18 Micro technologies

K. W. Chen, Y. L. Wang, L. Chang, C. W. Liu, Y. K. Lin, T. C. Wang, S. T. Chang, K. Y. Lo

研究成果: Conference article同行評審

1 引文 斯高帕斯(Scopus)


The low-K films and higher multiple stacked layers would be widely applied for ultra large-scale integrated circuits. However, for 8″; (200mm) or 12″ (300mm) wafer, the phenomena of wafer edge collapsing in higher interlayer low-K dielectric film causes front CMP polishing effect. (Shown in Fig. 1). Conventionally a amount of work has been developed in the optimization of different parameters, such as low pressure and high speed, metal dummy filling, harder pad used, and design of polishing head in order to resolve the problems. But these methods only engaged in design of experiment, not addressed in CMP theory of edge collapsing and controlling way. In this paper we will discuss the theory applied in Preston equation to explain the polishing behaviour in wafer edge. In advance, to implement the theory, we adopted novel strategies, including of different polishing head (sweep) vibration and pad edge sprayer methods, even new wafer retaining ring design and novel delivery slurry methods in advance. The characteristics of within wafer nonuniformity and edge profile against CMP polishing low-k films, fluorinated silicate glass (FSG). would be evaluated in this new strategy action. Besides, the dimension of metal line and VIA, and edge die-yield can be directly responded to the edge profile improvement. Front the action results, the average 7-10% yield improvement of 0.18 technology can be achieved, especially 15% edge-die yield improvement. The edge profile could promote the phenomena of no collapsing from the original 75 mm to 95 mm of wafer center-to-edge distance, excluding 3 mm edge of 8-inch wafer. These high efficient strategies for within-wafer planarization and edge profile is also proven and fulfilled with the reducing over 50% VIA CD deviation on the rule of lithography.

頁(從 - 到)259-261
期刊IEEE International Symposium on Semiconductor Manufacturing Conference, Proceedings
出版狀態Published - 2001
事件IEEE International Symposium on Semiconductor Manufacturing (ISSIM) 2001 - San Jose, CA, United States
持續時間: 2001 10月 82001 10月 10

All Science Journal Classification (ASJC) codes

  • 電子、光磁材料
  • 一般工程
  • 工業與製造工程
  • 電氣與電子工程


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