TY - GEN
T1 - On-chip reference oscillators with process, supply voltage and temperature compensation
AU - Tsai, Chao Fang
AU - Li, Wan Jing
AU - Chen, Peng Yu
AU - Lin, Ying Zu
AU - Chang, Soon Jyh
PY - 2010
Y1 - 2010
N2 - Here we present the design and implementation of a 130-MHz on-chip reference oscillator in a 0.18-μm 1-ploy 6-metal digital CMOS process. To compensate for the influences on the oscillation frequency by process, supply voltage and temperature (PVT) variations, the oscillator uses a bias adjustment technique without BJT devices, on-chip inductors or external components. Measurements of 8 samples in the 0 to 100°C temperature range indicate an average deviation of ±4.99% in the oscillation frequency. The process-induced frequency deviation is ±1.13% across chips at room temperature. The deviation of frequency with 10% supply voltage variation is within ±5.4%.
AB - Here we present the design and implementation of a 130-MHz on-chip reference oscillator in a 0.18-μm 1-ploy 6-metal digital CMOS process. To compensate for the influences on the oscillation frequency by process, supply voltage and temperature (PVT) variations, the oscillator uses a bias adjustment technique without BJT devices, on-chip inductors or external components. Measurements of 8 samples in the 0 to 100°C temperature range indicate an average deviation of ±4.99% in the oscillation frequency. The process-induced frequency deviation is ±1.13% across chips at room temperature. The deviation of frequency with 10% supply voltage variation is within ±5.4%.
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U2 - 10.1109/ISNE.2010.5669186
DO - 10.1109/ISNE.2010.5669186
M3 - Conference contribution
AN - SCOPUS:78751562689
SN - 9781424466948
T3 - 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
SP - 108
EP - 111
BT - 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
T2 - 2010 International Symposium on Next-Generation Electronics, ISNE 2010
Y2 - 18 November 2010 through 19 November 2010
ER -