On-chip reference oscillators with process, supply voltage and temperature compensation

Chao Fang Tsai, Wan Jing Li, Peng Yu Chen, Ying Zu Lin, Soon-Jyh Chang

研究成果: Conference contribution

10 引文 斯高帕斯(Scopus)

摘要

Here we present the design and implementation of a 130-MHz on-chip reference oscillator in a 0.18-μm 1-ploy 6-metal digital CMOS process. To compensate for the influences on the oscillation frequency by process, supply voltage and temperature (PVT) variations, the oscillator uses a bias adjustment technique without BJT devices, on-chip inductors or external components. Measurements of 8 samples in the 0 to 100°C temperature range indicate an average deviation of ±4.99% in the oscillation frequency. The process-induced frequency deviation is ±1.13% across chips at room temperature. The deviation of frequency with 10% supply voltage variation is within ±5.4%.

原文English
主出版物標題2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program
頁面108-111
頁數4
DOIs
出版狀態Published - 2010 十二月 1
事件2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Kaohsiung, Taiwan
持續時間: 2010 十一月 182010 十一月 19

出版系列

名字2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program

Other

Other2010 International Symposium on Next-Generation Electronics, ISNE 2010
國家Taiwan
城市Kaohsiung
期間10-11-1810-11-19

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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