On feasibility of HOY - A wireless test methodology for VLSI chips and wafers

Po Kai Chen, Yu Tsao Hsing, Cheng Wen Wu

研究成果: Conference contribution

8 引文 斯高帕斯(Scopus)

摘要

As we enter the deep submicron age, it is getting harder for traditional test equipments to catch up with the increasing speed, pin count, and parameter accuracy of new products. The rapid growth of test cost for semiconductor chips and wafers thus has become a wide concern. To solve this issue, we propose HOY - a novel wireless test system. HOY is under development, but preliminary feasibility study has been done. In this paper we present some economics models and simulation results, which show that HOY will be much more cost-effective than traditional testers.

原文English
主出版物標題2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
頁面243-246
頁數4
DOIs
出版狀態Published - 2007 十月 1
事件2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan
持續時間: 2007 四月 262007 四月 28

出版系列

名字2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Other

Other2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
國家/地區Taiwan
城市Hsinchu
期間07-04-2607-04-28

All Science Journal Classification (ASJC) codes

  • 硬體和架構
  • 電氣與電子工程

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