On feasibility of HOY - A wireless test methodology for VLSI chips and wafers

Po Kai Chen; Yu Tsao Hsing; Cheng Wen Wu

doi:10.1109/VDAT.2006.258170

On feasibility of HOY - A wireless test methodology for VLSI chips and wafers

Po Kai Chen, Yu Tsao Hsing, Cheng Wen Wu

電機工程學系

研究成果: Conference contribution

8 引文斯高帕斯（Scopus）

摘要

As we enter the deep submicron age, it is getting harder for traditional test equipments to catch up with the increasing speed, pin count, and parameter accuracy of new products. The rapid growth of test cost for semiconductor chips and wafers thus has become a wide concern. To solve this issue, we propose HOY - a novel wireless test system. HOY is under development, but preliminary feasibility study has been done. In this paper we present some economics models and simulation results, which show that HOY will be much more cost-effective than traditional testers.

原文	English
主出版物標題	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
頁面	243-246
頁數	4
DOIs	https://doi.org/10.1109/VDAT.2006.258170
出版狀態	Published - 2007 10月 1
事件	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan 持續時間: 2007 4月 26 → 2007 4月 28

出版系列

名字	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Other

Other	2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
國家/地區	Taiwan
城市	Hsinchu
期間	07-04-26 → 07-04-28

All Science Journal Classification (ASJC) codes

硬體和架構
電氣與電子工程

存取文件

10.1109/VDAT.2006.258170

其它文件與鏈接

引用此

Chen, P. K., Hsing, Y. T., & Wu, C. W. (2007). On feasibility of HOY - A wireless test methodology for VLSI chips and wafers. 於 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (頁 243-246). [4027542] (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258170

Chen, Po Kai ; Hsing, Yu Tsao ; Wu, Cheng Wen. / On feasibility of HOY - A wireless test methodology for VLSI chips and wafers. 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. 頁 243-246 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

@inproceedings{a8b5733501444dec974dcfbd592fa71d,

title = "On feasibility of HOY - A wireless test methodology for VLSI chips and wafers",

abstract = "As we enter the deep submicron age, it is getting harder for traditional test equipments to catch up with the increasing speed, pin count, and parameter accuracy of new products. The rapid growth of test cost for semiconductor chips and wafers thus has become a wide concern. To solve this issue, we propose HOY - a novel wireless test system. HOY is under development, but preliminary feasibility study has been done. In this paper we present some economics models and simulation results, which show that HOY will be much more cost-effective than traditional testers.",

author = "Chen, {Po Kai} and Hsing, {Yu Tsao} and Wu, {Cheng Wen}",

year = "2007",

month = oct,

day = "1",

doi = "10.1109/VDAT.2006.258170",

language = "English",

isbn = "1424401798",

series = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

pages = "243--246",

booktitle = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers",

note = "2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 ; Conference date: 26-04-2007 Through 28-04-2007",

}

Chen, PK, Hsing, YT & Wu, CW 2007, On feasibility of HOY - A wireless test methodology for VLSI chips and wafers. 於 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers., 4027542, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers, 頁 243-246, 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006, Hsinchu, Taiwan, 07-04-26. https://doi.org/10.1109/VDAT.2006.258170

On feasibility of HOY - A wireless test methodology for VLSI chips and wafers. / Chen, Po Kai; Hsing, Yu Tsao; Wu, Cheng Wen.
2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 243-246 4027542 (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers).

研究成果: Conference contribution

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AU - Hsing, Yu Tsao

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N2 - As we enter the deep submicron age, it is getting harder for traditional test equipments to catch up with the increasing speed, pin count, and parameter accuracy of new products. The rapid growth of test cost for semiconductor chips and wafers thus has become a wide concern. To solve this issue, we propose HOY - a novel wireless test system. HOY is under development, but preliminary feasibility study has been done. In this paper we present some economics models and simulation results, which show that HOY will be much more cost-effective than traditional testers.

AB - As we enter the deep submicron age, it is getting harder for traditional test equipments to catch up with the increasing speed, pin count, and parameter accuracy of new products. The rapid growth of test cost for semiconductor chips and wafers thus has become a wide concern. To solve this issue, we propose HOY - a novel wireless test system. HOY is under development, but preliminary feasibility study has been done. In this paper we present some economics models and simulation results, which show that HOY will be much more cost-effective than traditional testers.

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M3 - Conference contribution

AN - SCOPUS:34748875279

SN - 1424401798

SN - 9781424401796

T3 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

SP - 243

EP - 246

BT - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

T2 - 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006

Y2 - 26 April 2007 through 28 April 2007

ER -

Chen PK, Hsing YT, Wu CW. On feasibility of HOY - A wireless test methodology for VLSI chips and wafers. 於 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers. 2007. p. 243-246. 4027542. (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). doi: 10.1109/VDAT.2006.258170

On feasibility of HOY - A wireless test methodology for VLSI chips and wafers

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