On line adaptive data compression chip using arithmetic codes

Jer-Min Jou, Shiann Rong Kuang, Yuh Lin Chen, Chung Yuan Chiang

研究成果: Conference article同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper describes the design and implementation of a CMOS VLSI chip for data compression and decompression using adaptive binary arithmetic codes. During the design process, the systematic design methodology of high level synthesis is applied so that both of the minimum of hardware resource and the maximum of processing speed about the chip are compromised soundly. The chip implements a new flexible modeler which estimates the probabilities of binary symbols efficiently using the table-look-up approach with 1024 bytes SRAM and 288 bytes ROM. An asynchronous interface circuit for I/O communication of the chip is designed, thus the I/O operation and compression operation in the chip can be done in parallel. The concept of design for testability is used and a full scan is implemented in the chip. A prototype 0.8-micro chip has been designed and verified, and fabricated by CIC, it occupies 4.2*4.5 mm2 of silicon area. The chip can yield a compression and decompression rate of 3 Mbits/sec with a clock rate of 25 MHz.

原文English
頁(從 - 到)360-363
頁數4
期刊Proceedings - IEEE International Symposium on Circuits and Systems
4
出版狀態Published - 1996 一月 1
事件Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA
持續時間: 1996 五月 121996 五月 15

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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