On the design of a fault-tolerant systolic array multiplier using time redundancy

T.-Y. Chang, C.-C. Wang, J.-B. Shu, Cheng-Wen Wu

研究成果: Conference contribution

原文English
主出版物標題International Symposium on IC Design and Manufacturing (ISIC)
出版地Singapore
頁面497-502
出版狀態Published - 1991 九月

引用此

Chang, T-Y., Wang, C-C., Shu, J-B., & Wu, C-W. (1991). On the design of a fault-tolerant systolic array multiplier using time redundancy. 於 International Symposium on IC Design and Manufacturing (ISIC) (頁 497-502).