On the design of a fault-tolerant systolic array multiplier using time redundancy

T.-Y. Chang, C.-C. Wang, J.-B. Shu, Cheng-Wen Wu

研究成果: Conference contribution

原文English
主出版物標題International Symposium on IC Design and Manufacturing (ISIC)
出版地Singapore
頁面497-502
出版狀態Published - 1991 9月

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