On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation

Kuen Jong Lee, Jing Jou Tang, Wern Yih Duh

研究成果: Conference article同行評審

2 引文 斯高帕斯(Scopus)

摘要

An accurate threshold voltage determination method for CMOS gates is presented that can be used to enhance the performance of test generation (TPG) and fault simulation (FS). By using this model the `Byzantine General' problem during the FS and TPG can be overcome. Experimental data show that SPICE like accuracy can be achieved without carrying out circuit-level simulation.

原文English
頁(從 - 到)113-118
頁數6
期刊Proceedings of the Asian Test Symposium
出版狀態Published - 1998 十二月 1
事件Proceedings of the 1998 7th Asian Test Symposium - Singapore, Singapore
持續時間: 1998 十二月 21998 十二月 4

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程

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