On the high-performance Ti-salicide ULSI CMOS devices prepared by a borderless contact technique and double-implant structure

A borderless contact (BLC) technique and double-implant structure (DIS) have been developed successfully to fabricate high-performance Ti-salicide sub-quarter-micron CMOS devices. A SiO_xN_y film grown by low-temperature chemical vapour deposition is used to act as the selective etch-stop layer. The n⁺ and p⁺ DIS can reduce the junction leakage current which is usually enhanced by BLC etching near the edge of shallow trench isolation. Based on the use of the BLC process, the process window can be enlarged. In addition, the employed low-thermal oxynitride and high deposition rate can improve the salicide thermal stability and avoid the salicide agglomeration. Experimentally, by combining the BLC and DIS techniques, low leakage and low sheet resistance CMOS devices and low standby current and high yield 1 Mb SRAMs are fabricated successfully.