On the implementation of wave-pipelined multipliers in lookup table-based FPGAs

Yuan Shuenn Ke, Ming-Der Shieh, Ming Hwa Sheu

研究成果: Paper

摘要

In this paper, the performance evaluation and implementation of wave-pipelined multipliers in lookup table-based FPGAs are presented. Based on our proposed methodology, high-speed wave-pipelined multipliers have been successfully implemented in the Xilinx XC4000 series. The developed structure can be applied for the multiplication of two unsigned numbers or two two's complement numbers. Compared with the previous work, our measured results are better in terms of maximum difference of path delays, operating frequency, and the number of LUTs used. The results are promising and the design is well suitable for high-performance systems implemented in FPGAs.

原文English
頁面434-437
頁數4
出版狀態Published - 1997 十二月 1
事件7th International Symposium on IC Technology, Systems and Applications ISIC 97 - Singapore, Singapore
持續時間: 1997 九月 101997 九月 12

Other

Other7th International Symposium on IC Technology, Systems and Applications ISIC 97
國家Singapore
城市Singapore
期間97-09-1097-09-12

指紋

Table lookup
Field programmable gate arrays (FPGA)

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

引用此文

Ke, Y. S., Shieh, M-D., & Sheu, M. H. (1997). On the implementation of wave-pipelined multipliers in lookup table-based FPGAs. 434-437. 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.
Ke, Yuan Shuenn ; Shieh, Ming-Der ; Sheu, Ming Hwa. / On the implementation of wave-pipelined multipliers in lookup table-based FPGAs. 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.4 p.
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abstract = "In this paper, the performance evaluation and implementation of wave-pipelined multipliers in lookup table-based FPGAs are presented. Based on our proposed methodology, high-speed wave-pipelined multipliers have been successfully implemented in the Xilinx XC4000 series. The developed structure can be applied for the multiplication of two unsigned numbers or two two's complement numbers. Compared with the previous work, our measured results are better in terms of maximum difference of path delays, operating frequency, and the number of LUTs used. The results are promising and the design is well suitable for high-performance systems implemented in FPGAs.",
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Ke, YS, Shieh, M-D & Sheu, MH 1997, 'On the implementation of wave-pipelined multipliers in lookup table-based FPGAs', 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore, 97-09-10 - 97-09-12 頁 434-437.

On the implementation of wave-pipelined multipliers in lookup table-based FPGAs. / Ke, Yuan Shuenn; Shieh, Ming-Der; Sheu, Ming Hwa.

1997. 434-437 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.

研究成果: Paper

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Ke YS, Shieh M-D, Sheu MH. On the implementation of wave-pipelined multipliers in lookup table-based FPGAs. 1997. 論文發表於 7th International Symposium on IC Technology, Systems and Applications ISIC 97, Singapore, Singapore.