One-dimensional approach for floating field limiting ring enhanced high-voltage power transistor design

B. D. Liu, C. T. Sune

研究成果: Article同行評審

3 引文 斯高帕斯(Scopus)

摘要

A new analytic method that combines models of a plane junction in bulk and a cylindrical junction at a surface, is proposed. From this analysis, the optimal space between the base junction and the floating field limiting ring of a power transistor are obtained. The influences of the concentration and thickness of a lightly doped collector layer, the base junction depth and the applied voltage on the optimal space are also discussed. The deviation between the results obtained from this model and two-dimensional numerical solutions is within 5%. Experimental results obtained using high-voltage power transistors based on this approach are in agreement with theoretical predictions.

原文English
頁(從 - 到)891-899
頁數9
期刊International Journal of Electronics
66
發行號6
DOIs
出版狀態Published - 1989 六月

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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