Optimal design and performance assessment of extremely-scaled Si nanowire FET on insulator

Chun Yu Chen, Yi Bo Liao, Meng Hsueh Chiang, Keunwoo Kim, Wei Chou Hsu, Shiou Ying Cheng

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

Optimal design for nanowire FETs beyond 22 nm technology node is presented using numerical 3D simulation and physical analysis. Our results suggest that design optimization associated with the wire diameter could achieve performance benefits in the nanowire FET technologies. Small wire diameter is not necessary for performance, though it favors device scaling.

原文English
主出版物標題2009 IEEE International SOI Conference
DOIs
出版狀態Published - 2009
事件2009 IEEE International SOI Conference - Foster City, CA, United States
持續時間: 2009 十月 52009 十月 8

出版系列

名字Proceedings - IEEE International SOI Conference
ISSN(列印)1078-621X

Other

Other2009 IEEE International SOI Conference
國家United States
城市Foster City, CA
期間09-10-0509-10-08

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

指紋 深入研究「Optimal design and performance assessment of extremely-scaled Si nanowire FET on insulator」主題。共同形成了獨特的指紋。

引用此