@inproceedings{63ae9ed95f0943ccbadea8e41298c083,
title = "Optimal design and performance assessment of extremely-scaled Si nanowire FET on insulator",
abstract = "Optimal design for nanowire FETs beyond 22 nm technology node is presented using numerical 3D simulation and physical analysis. Our results suggest that design optimization associated with the wire diameter could achieve performance benefits in the nanowire FET technologies. Small wire diameter is not necessary for performance, though it favors device scaling.",
author = "Chen, {Chun Yu} and Liao, {Yi Bo} and Chiang, {Meng Hsueh} and Keunwoo Kim and Hsu, {Wei Chou} and Cheng, {Shiou Ying}",
year = "2009",
doi = "10.1109/SOI.2009.5318741",
language = "English",
isbn = "9781424452323",
series = "Proceedings - IEEE International SOI Conference",
booktitle = "2009 IEEE International SOI Conference",
note = "2009 IEEE International SOI Conference ; Conference date: 05-10-2009 Through 08-10-2009",
}