Origin of stress memorization mechanism in strained-Si nMOSFETs using a low-cost stress-memorization technique

Yao Tsung Huang, San Lein Wu, Shoou Jinn Chang, Cheng Wen Kuo, Ya Ting Chen, Yao Chin Cheng, Osbert Cheng

研究成果: Article

6 引文 斯高帕斯(Scopus)

摘要

Implementation of strained-Si MOSFETs with optimum low-cost stress-memorization technique for a 40-nm technology CMOS process was demonstrated. Devices fabricated on (100) substrate with 100channel orientation provide additional 8% current drivability improvement for strained-Si nMOSFETs without any degradation of pMOSFETs performance. The stress-memorization technique (SMT) mechanism was experimentally verified by studying the impact of layout geometry (length of source/drain LS/D and polyspacing) on the device performance. In the SMT devices with LS/D down to 0.11 m and polyspace reduced to 120 nm, no obvious current improvement and more performance degradation are observed compared with control device (only strained contact etch-stop layer), indicating that the benefit of the SMT is substantially eliminated and showing that the SMT-induced stress is mainly originated from the source/drain region in our case.

原文English
文章編號5678837
頁(從 - 到)1053-1058
頁數6
期刊IEEE Transactions on Nanotechnology
10
發行號5
DOIs
出版狀態Published - 2011 九月

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

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