Output bit selection methodology for test response compaction

Wei Cheng Lien, Kuen Jong Lee

研究成果: Conference contribution

摘要

In this paper we propose an output-bit selection technique for test response compaction, with which only a subset of output response bits is selected for observation during testing. Advantages of this technique include zero aliasing, high compaction ratio, full X-Tolerance, low area overhead, simple test control and high diagnosability. Also no circuit/ ATPG modification is needed, hence this work can be easily integrated into any typical industrial design/test flow to significantly reduce test cost. Experimental results show that in general less than 10% of test response data of already very compact test sets are needed to detect all testable stuck-At or transition faults, with the reduction ratio increasing with the size of circuits, e.g., only 1.27% of output bits need be observed for b19 that contains more than 1M faults. Efficient test architectures to implement this technique are also presented, which include one that can deal with test responses containing high percentage of unknown values.

原文English
主出版物標題Proceedings - 2016 IEEE International Test Conference, ITC 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781467387736
DOIs
出版狀態Published - 2016 7月 2
事件47th IEEE International Test Conference, ITC 2016 - Fort Worth, United States
持續時間: 2016 11月 152016 11月 17

出版系列

名字Proceedings - International Test Conference
0
ISSN(列印)1089-3539

Other

Other47th IEEE International Test Conference, ITC 2016
國家/地區United States
城市Fort Worth
期間16-11-1516-11-17

All Science Journal Classification (ASJC) codes

  • 電氣與電子工程
  • 應用數學

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