Output-bit selection with X-avoidance using multiple counters for test-response compaction

Wei Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong Yu Hsieh

研究成果: Conference contribution

3 引文 斯高帕斯(Scopus)

摘要

Output-bit selection is a recently proposed test-response compaction approach that can effectively deal with aliasing, unknown-value, and low-diagnosis problems. This approach has been implemented using a single counter and a multiplexer without considering unknown values. Also, such an implementation may require the application of a pattern multiple times in order to observe all selected responses. In this paper, we present a multiple-counter-based architecture with a new selection algorithm that can avoid most unknown-values yet achieve high compaction ratio. The remaining small number of unknowns can then be dealt with using some simple masking logic. Experiments on IWLS'05 circuits show that even with 16% unknown responses, all unknown values can be handled with 88.92%93.21% response-volume reduction still achieved and only a moderate increase in test-application time.

原文English
主出版物標題Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014
發行者IEEE Computer Society
ISBN(列印)9781479934157
DOIs
出版狀態Published - 2014 一月 1
事件19th IEEE European Test Symposium, ETS 2014 - Paderborn, Germany
持續時間: 2014 五月 262014 五月 30

出版系列

名字Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014

Other

Other19th IEEE European Test Symposium, ETS 2014
國家Germany
城市Paderborn
期間14-05-2614-05-30

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality

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  • 引用此

    Lien, W. C., Lee, K-J., Chakrabarty, K., & Hsieh, T. Y. (2014). Output-bit selection with X-avoidance using multiple counters for test-response compaction. 於 Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014 [6847823] (Proceedings - 2014 19th IEEE European Test Symposium, ETS 2014). IEEE Computer Society. https://doi.org/10.1109/ETS.2014.6847823