Output selection for test response compaction based on multiple counters

Wei Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong Yu Hsieh

研究成果: Conference contribution

2 引文 斯高帕斯(Scopus)

摘要

Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%∼67.87% test application time with only slight increase on area overhead.1

原文English
主出版物標題Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
發行者IEEE Computer Society
ISBN(列印)9781479927760
DOIs
出版狀態Published - 2014 一月 1
事件2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan
持續時間: 2014 四月 282014 四月 30

出版系列

名字Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Other

Other2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
國家Taiwan
城市Hsinchu
期間14-04-2814-04-30

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering

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  • 引用此

    Lien, W. C., Lee, K-J., Chakrabarty, K., & Hsieh, T. Y. (2014). Output selection for test response compaction based on multiple counters. 於 Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 [6834865] (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-DAT.2014.6834865