P-39: A highly stable a-Si:H TFT gate driver circuit with reducing clock duty ratio

Chih Lung Lin; Chun Da Tu; Min Chin Chuang; Kuan Wen Chou; Chia Che Hung; Chih Wei Wang; Min Feng Chiang; Yung Chih Chen

doi:10.1889/1.3499952

P-39: A highly stable a-Si:H TFT gate driver circuit with reducing clock duty ratio

Chih Lung Lin
, Chun Da Tu
, Min Chin Chuang
, Kuan Wen Chou
, Chia Che Hung
, Chih Wei Wang
, Min Feng Chiang
, Yung Chih Chen

電機工程學系

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

摘要

This paper presents a new a-Si:H gate driver circuit for large panel applications. Consisting of 12 TFTs and three capacitors, the proposed circuit is fabricated for measurement. The threshold voltage shift of TFTs is significantly reduced by reducing clock duty ratio. Experimental results indicate that the gate driver circuit operates stably under long-term and high temperature testing.

原文	English
頁（從 - 到）	1360-1362
頁數	3
期刊	Digest of Technical Papers - SID International Symposium
卷	41 1
DOIs	https://doi.org/10.1889/1.3499952
出版狀態	Published - 2010 5月

All Science Journal Classification (ASJC) codes

一般工程

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10.1889/1.3499952

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abstract = "This paper presents a new a-Si:H gate driver circuit for large panel applications. Consisting of 12 TFTs and three capacitors, the proposed circuit is fabricated for measurement. The threshold voltage shift of TFTs is significantly reduced by reducing clock duty ratio. Experimental results indicate that the gate driver circuit operates stably under long-term and high temperature testing.",

author = "Lin, \{Chih Lung\} and Tu, \{Chun Da\} and Chuang, \{Min Chin\} and Chou, \{Kuan Wen\} and Hung, \{Chia Che\} and Wang, \{Chih Wei\} and Chiang, \{Min Feng\} and Chen, \{Yung Chih\}",

year = "2010",

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AU - Tu, Chun Da

AU - Chuang, Min Chin

AU - Chou, Kuan Wen

AU - Hung, Chia Che

AU - Wang, Chih Wei

AU - Chiang, Min Feng

AU - Chen, Yung Chih

PY - 2010/5

Y1 - 2010/5

N2 - This paper presents a new a-Si:H gate driver circuit for large panel applications. Consisting of 12 TFTs and three capacitors, the proposed circuit is fabricated for measurement. The threshold voltage shift of TFTs is significantly reduced by reducing clock duty ratio. Experimental results indicate that the gate driver circuit operates stably under long-term and high temperature testing.

AB - This paper presents a new a-Si:H gate driver circuit for large panel applications. Consisting of 12 TFTs and three capacitors, the proposed circuit is fabricated for measurement. The threshold voltage shift of TFTs is significantly reduced by reducing clock duty ratio. Experimental results indicate that the gate driver circuit operates stably under long-term and high temperature testing.

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M3 - Article

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JO - Digest of Technical Papers - SID International Symposium

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P-39: A highly stable a-Si:H TFT gate driver circuit with reducing clock duty ratio

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