P-50: Power consumption ameliorated for integrated gate driver circuit with low frequency clock

Chih Lung Lin, Chun Da Tu, Chia Che Hung, Mao Hsun Cheng, Chia En Wu, Yung Chih Chen

研究成果: Conference article同行評審

2 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel low power consumption gate driver circuit with 12 TFTs and one capacitor which is made by hydrogenated amorphous silicon technology. The pull-down structure can not only prevent the floating of gate lines, but also suppress the threshold voltage shift of a-Si:H TFTs. According to the measurement results, the proposed gate driver circuit can be operated stably more than 10 days at high temperature (T = 100 ° C). Furthermore, the power consumption of the proposed gate driver circuit can be reduced 52.6% compared to the previously proposed gate driver circuit.

原文English
頁(從 - 到)1285-1287
頁數3
期刊Digest of Technical Papers - SID International Symposium
42 1
DOIs
出版狀態Published - 2011 六月

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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