This paper describes the design and implementation of a parallel structured transport station for a heterogeneous microcomputer network. The connected transport stations provide a reliable and efficient end-to-end transport service between processes in different nodes. A 2 plus one-half bus achitecture is designed to provide high speed parallel processing capability and let the transport station be easily installed in a host microcomputer through the common memory & bus coupling mechanism. The hardware configuration is described. A communication nucleus has also been designed to support a multi-tasking environment for the development of a more flexible protocol software. The software structure is also presented. The concept & technology have been applied to many systems, such as Multibus, STD bus, S-100 bus based microcomputers, to support the experimental local area network.
|主出版物標題||Unknown Host Publication Title|
|編輯||Kane H. Kim, K. Chon, C.V. Ramamoorthy|
|出版狀態||Published - 1986 十二月 1|
All Science Journal Classification (ASJC) codes