A system for automatic scheduling and sharing data paths has been developed. It is generic; different design styles such as pipeline, chaining, loop pipelines, etc., have been considered, and solutions of fastest possible, cheapest possible, fastest within hardware constraints, or lowest cost within time constraint could be found according to the user's request. The entire design space then could be explored with it. The scheduling algorithm is stepwise selective, dealing with hardware urgency, time urgency, interconnection urgency, data urgency, and control urgency in a serial method with multiple levels of selections. the concept of the sharing algorithm is to consider the inter-influenced properties between operator-sharing and register-sharing, construct two inter-involved sharing criteria for them simultaneously, and then merge them concurrently.
|頁（從 - 到）||1769-1772|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||Published - 1991 十二月 1|
|事件||1991 IEEE International Symposium on Circuits and Systems Part 4 (of 5) - Singapore, Singapore|
持續時間: 1991 六月 11 → 1991 六月 14
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering